The present invention relates to a semiconductor memory device having a floating gate structure and a method of manufacturing the same.
An EPROM (electrically programmable read only memory) shown in FIG. 1, for example, is known as a conventional semiconductor memory device having a floating gate structure. The EPROM shown in FIG. 1 is manufactured by the steps shown in FIGS. 2A to 2C.
As shown in FIG. 2A, first thermal oxide film 2 is formed on an island-like element region on p.sup.- -type silicon substrate 1 surrounded by field oxide film 1a. First polysilicon film 3, which will be formed into a floating gate electrode, is formed on the entire surface of second thermal oxide film 2 using the CVD (chemical vapor deposition) method. Thereafter, a phosphorous is doped into first polysilicon film 3. Then, the resultant structure is thermally oxidized at a low temperature of, e.g., 1,000.degree. C. or below to form second thermal oxide film 4 on first polysilicon film 3. Second polysilicon film 5, which will be formed into a control gate electrode, is formed on the entire surface of second thermal oxide film 4 using the CVD method. Then, a phosphorous is doped into second polysilicon film 5. Thereafter, as shown in FIG. 2B, photoresist film 6 having a predetermined pattern is formed on second polysilicon film 5. Films 5, 4, 3, and 2 are sequentially etched using photoresist film 6 as a mask to form first gate oxide film 12, floating gate electrode 13, second gate oxide film 14, and control gate electrode 15. An n-type impurity such as As ions is implanted in substrate 1 at a high concentration using this multilayer as a mask. Then, the resultant structure is thermally oxidized to form thermal oxide film 7 on the entire surface of the multilayer and exposed portions of substrate 1, as shown in FIG. 2C, while the implanted As ions are activated to form n.sup.+ -type drain and source regions 8 and 9. Thereafter, for example, PSG film 10 serving as a passivation film is formed on the entire surface of the resultant structure. PSG film 10 and thermal oxide film 7 are selectively etched to form contact holes (not shown) leading to drain and source regions 8 and 9, respectively. In addition, an Al-Si film (not shown) is formed on the entire surface of the resultant structure. The Al-Si film is patterned to form source electrode 11 (FIG. 1) and drain electrode 12 (both of which are not shown in FIG. 2C, but are respectively denoted by reference numbers 11 and 12 in FIG. 1). With the above process, the EPROM cell shown in FIG. 1 is manufactured.
In the above-described EPROM, electrons are injected into floating gate electrode 13 by applying a positive high voltage to n.sup.+ -type drain region 8 and control gate electrode 15, thereby writing data.
However, if a positive high voltage is applied for some reason to control gate electrode 15 after writing of data, the electrons injected into floating gate electrode 13 are attracted by control gate electrode 15 through the second thermal oxide film, and hence escape from floating gate electrode 13. For this reason, the data may not be retained.
Such an escape of electrons occurs because the breakdown voltage of second thermal oxide film 14 is low. The breakdown voltage is low for the following reason.
First polysilicon film 3 serving as the floating gate electrode is composed of grains having various crystal orientations. For this reason, if first polysilicon film 3 is thermally oxidized at a low temperature of 1,000.degree. C. or below to form second thermal oxide film 4 serving as second thermal oxide film 14, surface asperity appears at the interface between floating gate electrode 13 and second gate oxide film 14, resulting in a decrease in breakdown voltage of second thermal oxide film 14. Such a problem caused by low-temperature thermal oxidation can be eliminated by thermally oxidizing second thermal oxide film 4 at a high temperature of 1,100.degree. C. or higher instead of at low temperature. However, in high-temperature thermal oxidation, a predetermined junction position may be changed, or a wafer may be warped. As a result, the performance of the semiconductor memory device is degraded, and the yield is decreased.